The present invention relates in general to communication systems and components, and is particularly directed to a new and improved current mode analog-to-digital (A/D) converter, containing a cascaded arrangement of threshold detector bit cells that are driven by a transconductance amplifier architecture of the type described in my above-referenced ""408 application, that is capable of very fast conversion times due to its substantially instantaneously propagated current mode operation, very limited voltage deflections and lack of feedback requirements.
Due to the extremely rapid advancement of digital signal processing technologies, many if not most signal processing systems and networks are currently (and can be expected to continue to be) designed to operate in the digital domain. As the raw signals input to these systems and networks are analog, a critical component at the front end of the overall signal flow path is the analog-to-digital converter, which quantizes the analog signal into a form suitable for digital processing.
A particularly attractive type of A/D converter that has been proposed for low voltage overhead, high speed signal processing applications, such as but not limited to telecommunication networks, is a pipelined architecture that uses differential current mode techniques. Among the advantages of this type of converter are inherent low voltage swing and the elimination of the need for linear capacitors. (For a non-limiting example of documentation that describes the general architecture and benefits of a pipelined, differential current mode-based A/D converter, attention may be directed to an article by Chung-Yu Wu et al, entitled: xe2x80x9cA CMOS Transistor-Only 8-b 4.5-Ms/s Pipelined Analog-to-Digital Converter Using Fully-Differential Current-Mode Circuit Techniques,xe2x80x9d IEEE Journal of Solid-Stage Circuits, Vol. 30, No. 5, May, 1995, pp. 522-532.)
In accordance with the present invention advantage is taken of the performance and signal processing functionality of the transconductance amplifier circuit disclosed in the above-referenced ""408 application, to realize a substantially improved A/D converter architecture implemented as a cascaded arrangement of current mode-based threshold detector bit cells. The A/D converter of the invention is capable of very fast conversion times due to its substantially instantaneously propagated current mode operation, very limited voltage deflections and lack of feedback requirements, making it attractive for high speed signal processing applications, such as, but not limited to, telecommunication modem chips.
Although it has a multi-bit cell or multistage cascaded configuration, the current mode A/D converter architecture of the present invention is not xe2x80x98pipelinedxe2x80x99 in the customary sense; in the cascaded architecture of the invention, there is no sampling delay associated with each successive bit-stage of the converter. Instead, when an input voltage Vin representative of an analog quantity to be digitized is applied to an upstream-most or front end transconductance-based stage of the converter""s cascaded sequence of bit cells, the only delay encountered is that associated with the electronic propagation delays through the electronic components in the xe2x80x98ripplingxe2x80x99 path along the downstream threshold-based bit cells. There is no sample and store operation in any cell, so that there is no associated storage delay as is customarily encountered in a conventional xe2x80x98pipelinedxe2x80x99 architecture.
The A/D converter architecture of the invention has a front end stage which receives an input voltage Vin representative of the quantity Q to be digitized, and outputs a pair of output currents to a first or most significant bit (MSB)-associated one of Nxe2x88x921 cascaded, identically configured A/D (threshold comparator-based) bit cells, where N corresponds to the digital code (number of bits) resolution of the A/D converter. In accordance with a non-limiting but preferred implementation, the front end stage contains a transconductance amplifier circuit of the type described in the foregoing ""408 application. It also includes circuitry that generates a set of accurate and stable reference voltage and currents used by the circuitry of each downstream A/D cell to resolve its respective bit.
A respective current threshold-based ith A/D cell outputs a single ith digital bit (either a xe2x80x981xe2x80x99 or a xe2x80x980xe2x80x99) of the overall N-bit digital code output of the converter and also couples a pair of output currents to the next (i+1)th A/D cell. The last or Nxe2x88x921th A/D cell of the cascaded bit cells is configured to provide both the next to least significant bit and the least significant bit (LSB) of the resolved N bit code.
For this purpose, a respective A/D xe2x80x98bitxe2x80x99 cell has first and second current input ports, respectively coupled to the first and second current output ports of the immediately preceding bit cell. The first current input port is coupled to a thresholding reference node, which is coupled to a first leg or side of a Darlington-configured differential transistor pair-based, bit-resolving circuit, and to a first leg or side of a Darlington-configured differential transistor pair-based, current-steering circuit.
The bit-resolving differential pair is operative to selectively establish the state of the cell""s output bit, based on whether the value of the first input current is at least equal to the value of the copy of a reference current supplied to each cell from the front end stage. The current-steering differential pair selectively controls the mirroring of the value of the second input current, either as is, to each of the first and second current output ports, or steers the difference between the first input current and the reference current to current mirror circuitry for production of mirrored currents proportional to this difference for application to the next downstream cell.
If the value of the input currents is equal to or greater than the reference current, the current-steering circuit diverts the second input current to a voltage supply rail, so that the second input current cannot be coupled to the current mirror. In addition, the bit-resolving circuit steers the bias current in a manner that causes a high (xe2x80x981xe2x80x99) logic level to be applied to the bit output terminal of that cell. On the other hand, if the value of the input current is less than the reference current, the current-steering circuit applies the second input current to the current mirror, while the bit-resolving circuit steers the bias current in a manner that causes a low (xe2x80x980xe2x80x99) logic level to be applied to the bit output terminal of that cell.